New Ocelot Chip Makes Strides in Quantum Computing

Reporting in the February 26 issue of the journal Nature, a team of scientists from AWS and Caltech demonstrate a new quantum chip architecture for suppressing errors using a type of qubit known as a cat qubit. Cat qubits were first proposed in 2001, and, since then, researchers have developed and refined them. Now, the AWS team has put together the first scalable cat qubit chip that can be used to efficiently reduce quantum errors. Called Ocelot, the new quantum computing chip is named after the spotted wild cat, while also giving a nod to internal “oscillator” technology that underlies the cat qubits.

“For quantum computers to be successful, we need error rates to be about a billion times better than they are today,” says Oskar Painter (PhD ’01), John G Braun Professor of Applied Physics and Physics at Caltech and head of quantum hardware at AWS. “Error rates have been going down about a factor of two every two years. At this rate, it would take us 70 years to get to where we need to be. Instead, we are developing a new chip architecture that may be able to get us there faster. That said, this is an early building block. We still have a lot of work to do.”

“We are on a long-term quest to build a useful quantum computer to do things even the best supercomputers cannot do, but scaling them up is a huge challenge,” says study co-author Fernando Brandão, Bren Professor of Theoretical Physics at Caltech and director of applied science at AWS. “So, we are trying new approaches to error correction that will reduce the overhead.”